IT@Intel: Increasing EDA Performance and Throughput with the Intel Xeon Processor Scalable Family

February 17th, 2022 |
Image for FaceBook
Download PDFRead/Download White Paper (PDF)
 
Share this post:
Facebook | Twitter | Google+ | LinkedIn | Pinterest | Reddit | Email
 
This post can be linked to directly with the following short URL:


 
This pdf file can be linked to by copying the following URL:


 
Right/Ctrl-click to download the pdf file.
 
Subscribe:
Connected Social Media - iTunes | Spotify | Google | Stitcher | TuneIn | Twitter | RSS Feed | Email
Intel - iTunes | Spotify | RSS Feed | Email
Intel IT - iTunes | Spotify | RSS Feed | Email
 

IT Best Practices: Intel IT operates 56 data center modules at 16 data center sites. These sites have a total capacity of 103 megawatts, housing more than 360,000 servers that underpin the computing needs of 116,000 employees. Intel IT has four main segments of operation: Design, Office, Manufacturing and Enterprise. This paper focuses on only the Design segment.

Intel’s silicon Design engineers need significant increases in computing capacity to deliver each new generation of silicon chips. To meet those requirements, Intel IT conducts ongoing throughput performance tests using real-world Intel silicon Design workloads. These tests measure Electronic Design Automation (EDA) workload throughput and help us analyze the performance improvements—and in turn, business benefit offered by newer generations of Intel processors.


For more information on Intel IT Best Practices, please visit intel.com/IT
 

Tags: , , , , , , , , , ,
 
Posted in: data centers, Intel, Intel IT, IT White Papers, IT@Intel