High Demand for Low Power

January 29th, 2007 |
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Low power is becoming more and more popular in the design community, pushing designers to become more and more creative. Neil Hand of Cadence gives us a look at  the technical considerations and hurdles, and a glance at what Cadence is doing to meet the needs of the marketplace.


Host: Paul Lancour – PodTech

Guest: Neil Hand – Cadence

Paul Lancour – PodTech

I’m Paul Lancour with PodTech.net and I’m here with Neil Hand. He’s the director of Vertical Solutions Marketing at Cadence. Neil, thanks for joining us.

Neil Hand – Cadence

Thank you.

Paul Lancour – PodTech

I want to start off by talking you about – this is the low power podcast and the first thing I want to ask you is, why low power has become such a hot topic in design community.

Neil Hand – Cadence

Well, there is a lot of reasons. The first and most obvious one is the increase in the use of mobile devices and the desire of people put more functionality in those devices as well as having longer battery life and so forth. But, there’s a lot of other factors apply there as well. Even for the non battery powered device as we put more functionality and we are increasing the power density it’s getting more and more difficult to build these devices within the specs that are required by the customer.

So, that can be cured correctly into the system can function correctly. So, this is driving it as well. And this is being made even worse as we go to smaller process geometries. As we go to the process geometry of 90 nanometers and below and specially at 65 nanometers what’s happening in the chips is a leakage current and the clocking are becoming the dominant power users in the designs and so what we need to do we start more actively managing the power in these devices otherwise we’re aren’t be going to manufacture or run the devices.

And so the traditional approaches that the people have used just to add on some power optimization in the life stage of the design flow are really not longer working. We have to build in power right from the get go as part of the design process so we can make sure that the designs both meet the requirements of the end product but also can be manufactured and manufactured within the constraints of the system that have been designed.

Paul Lancour – PodTech

So, it sounds like those are the forces in the market that are driving low power design and it sounds also like it’s pushing it up against the limits of the ability to design such low power devices. So, when considering low power, what kind of an impact does it have on design?

Neil Hand – Cadence

It really touches your every part of the design process if it’s done properly. When we think of low power what you really want to do is think of low power and not just as a what am I, how am I going to use a low power process from the vendor, (Inaudible) we really want to think of low power right from the architectural design of the chip all the way down to our vendor selection and implementation. And we need to consider it because any — if we don’t consider it through out the whole process, if we miss it just in one part of our design or verification activities, all of a sudden all of the good that we may have done in another part of the design process is going to be undone. So, we need to make sure that we take it into account through every stage of the design process.

Paul Lancour – PodTech

So, I imagine that create some significant challenges for the design team.

Neil Hand – Cadence

It does. So, typically the design team is your team is thinking is (Inaudible) about meeting timing, (Inaudible) about meeting area constraints getting timing and single integrity in closer. Now, we’re adding into that all of these power constraints. Is the device going to have to correct power utilization, as our leakage current being managed, is there are going to be any hotspots on the device itself? And so what we need to do is be able to try it off all of these different constraints against each other the area, the power and the timing. And the other challenge that we face is, that there is no common why or there has not been in the past to come a way of the power intend for device, for being used in the design process.

So, if in the early stages of the architecture you decide on a particular power implementation for the device, there is no way to capture that and follow it through the design process.

So, what it this means it becomes very hard to manage power through as the design evolves. And the other challenge is that as we go through this the RTL is no longer really the golden model because there is no way to capture this power intent of the design. We start using Adhawk techniques and having to put additional information into the RTL code, so where traditionally the RTL that’s created by a design as is the golden model for verification and for implementation that’s no longer the case. There might be multiple models of the design and what you implement and what you verify may no longer be the same thing.

Paul Lancour – PodTech

So, given everything you’ve outlined here, it’s amazing that anyone would be able to make a low power chip at all. How are people managing to do so?

Neil Hand – Cadence

It’s a mix of different methods a lot of it is this Adhawk techniques that people are implying, so, scripts that they’re using to convert data between different tools, manual insertion of capabilities into the design, scripts to automate that process and there’s also a lot of luck and a lot of hard work. It’s a lot of hard work by the design teams and the problem with all of this is it becomes very error-prone.

If you’re working with modifying a simulation model in order to simulates some of the effects of the low power, if you’re using these complex scripts and complex tools interactions there is going to be errors and you’re not going to know where those errors are, and the errors are going to show up when you actually get a chip and the chip goes is in the lab, and it either fails or it doesn’t meet your power specs and becomes a major problem for the design teams because they are not going to know this until after silicon is produced.

Paul Lancour – PodTech

So what’s Cadence doing to move from an Adhawk approach like this to employing this holistic approach?

Neil Hand – Cadence

Yeah, so what we’re trying to do or what we are doing is take — is as you mentioned, taking a holistic approach to the problem. Look at the full design challenges from your architecture designs through implementation, through verification and saying how do we have a way of capturing the power intent for the design and using that knowledge throughout the design — throughout the whole process.

So, having tools that work off this knowledge having a way of capturing that knowledge. And so key to that is a powerful method. You might have heard of or the listeners may have heard of, which is the common Power Format, CPF.

So, CPF is a way of capturing the power intent to the design and then all of the tools in the tool chain and then work of this Common Power Format to make sure that together with the design description in the form of RTL code you have a complete capture of both the design and the power intent, all of the tools are seeing the same design, is being optimized according to the power requirements, it’s being implemented according to the power requirements and also any of the logic that gets added to the design or any of the structures that are added to the design as part of the power process is also being verified to make sure that what we’re building is what we intended to build and so long before we get to silicon, we can identify problems, we can address them, but also more importantly, heavily automate the whole process so this significantly reduces the risk of adopting Low Power in the design.

Paul Lancour – PodTech

What role do standards play in this process?

Neil Hand – Cadence

So, standards are an important thing within the EDA world. Standards allow interaction between multiple people in the industry that enable the development in the evolution of methodologies and so part of the evolution of CPF has been — CPF was created through the powerful initiative, which is a correlation of 22 different companies both end users as well as industry, EDA partners.

They work together in real live design projects through multiple revisions of the standards, lots of feedback to develop a Common Power Format and this is the format that’s being used in production today and what we’ve done is we’ve taken this Common Power Format and the parser for the format and it’s being done added to Si2’s Low Power Coalition and SI2 have now approved the version 1.0 of the CPF format in January they have approved this as a standard and after I believe it’s a 60 day waiting period it will be released to all the members as a standard that can be used and we’re going to continue to work with Si2 to work with them to ensure that it becomes a single standardized power format that everyone can work towards.

Paul Lancour – PodTech

Can you give us some more specific, some examples of the technology that’s gone into creating the Cadence Low-Power solution?

Neil Hand – Cadence

Yeah, so there is a lot of cool technology that I could talk about; far more than we can talk about the time we’ve got here today. Yeah, so CPF is interesting because it is enabler to all the technology, but if all you’ve got it as a file format it’s not going to that interesting like it’s really interesting is lot of the cool technology that’s gone into the tools to enable a full low power flow and yeah if we take a few examples in verification, what we’ve been able to do in verification is create both simulation and using formal techniques a way of verifying the power intent of the design.

So, simulation for instance, if we put power shut-off into a design, where power shut-off is a technique where we can shut down part of a circuit to reduce the leakage current. Typically this is done as a process as we’re doing that implementation of a chip and it’s very hard to verify it. So, what we’ve done is within the simulation, the simulation environment can use the knowledge that’s in a CPF file and it can make the simulator behave as if the parts of the circuit are being powered-up in powered-down.

So, what this means if the part of the circuit is being powered-down, we will make sure that any logic that it’s reading from that circuit is going to have access putting into an unknown logic values driven into it. If you are driving logic into a powered-down portion, or values into a powered-down portion of the circuit, we’re going to make sure that that portion of the circuit isn’t going to be working, isn’t going to be accepting those values. If you’ve implemented stack retention, we’re going to simulate the correct behavior of that stack retention. All this is done using the standard verification environment, the standard design models, but bringing in the CPF, which is the power intent to the design and automating that whole process.

We also have the ability of using formal techniques, whether it’s the Incisive Formal Verify where we will be able to use formal techniques to make sure that insertions relating to the behavior of that low-power structures and the design are working correctly or can form a low-power where we can automate the process of making sure that the correct type of low-power structure has been added to the design. Our level shift is in the right place between our domains; are we getting the correct sequencing for powered-up and powered-down, of power shut-off sections of the circuit?

So, it’s really exciting because we can now take our existing environments and just by adding in the Common Power Format with all these technology that we’ve add into the verification tools or to make this whole process.

If we look at some of the other tools in the flow like, Synthesis, in Synthesis what we’re able to do, is do a lot of optimization to ensure out that we’re getting the best power in the final device that we can get and power is being taken into account together with our timing (Inaudible). We’re doing (Inaudible) against multiple timing — you have multiple constraints. Some examples of that is that why we can support your optimized clocking structures.

So, by using multi-level clock gating where we’re going to go in and we’re going to say, different parts of the circuit that are being gated of different structures. Can we combine those together and move what we call de-cloning, where we’re going to take clock gate and move them up through the clocking trees so we can shut down larger portions of the circuit, we can propagate those clocking equations further up the clock tree by doing what we call multi level clocking, where we’re going to find common terms and split the trees by extra flows common terms.

So, the maximum amount of logic in the circuit can be shut down and the clocking trees themselves can be shut down as I mentioned earlier, the clock trees and the leakage current are some of the major users of — or are the dominant users of power in the circuit. What we’ve also added is to support some of the more advanced low-power techniques something that’s called Dynamic Frequency and Voltage Scaling, where a circuit can adapt both its clock frequency and its operating voltage depending on the demands that are being placed on it, by the system itself and this is — proposes new challenges because you no longer have a single operating voltage or a single operating frequency you have many of them.

So what we are able to do in the Synthesis mode is actually take those and do multimode optimization. We can simultaneously optimize the design that we’re producing based of what are the many modes that this circuit can operate in, again trading of our power requirements with our area requirements and our timing requirements. I said some examples for Synthesis and across the whole flow there are even more thing. If you look at test, a design for test. One of the challenges people have when they are doing testing is as these devices get more and more power dense. It can become a problem to test them, if you power-up all of your demands simultaneously on a test and start testing it, you can actually have more power going into the circuit then — can be allowed in the circuit might fail on the test or it may even destroy the device on the tester.

So, by using power (Inaudible) tests, what we can do is we can go in and we can say while using the knowledge of what our power domains are and make sure that as we’re testing; we’re activating the correct power domains at the correct times; we’re optimizing the test patterns that we’re producing to make sure that they have the lowest possible power consumption for those test patterns. So, it’s a very cool technology that’s going to change the way people do test today.

We’ve got lots of cool technology in (Inaudible) in Cadence suite of tools where whether it’s automatic insertion of the level shifters, whether its automatic creation of the appropriate power domains, lots of stuff there, but one thing that I really like and it’s very popular amongst the customers that have seen it as well, one of the challenges you face as you built more and more complexity into the power domains of the design, you just start building the power grids onto the chip and the question becomes, how do I even know that my power that my power grid that I have created for the chip is even going to work. I have got multi-stage switches that are going to start turning on the power into my circuit, lots of different power domains, things going up and down all over the place, how do I know this is going to work?

So, we have a lot of cool technology based around Power Grid Sign-Off, where we can do transient power analysis. So, we can look at, how the device is powering up, how a different domains that are defined in the C profile are being switched-on and switched-off and making sure that our power grids are going to work as we expected and do all of the — we have voltage drop analysis across the whole chip and make sure everything remains within Spec and this is in addition to some of the traditional approaches of the static and dynamic analysis of the power and the design looking at both static, purely what it has my design structure but as well has dynamic power analysis where we’re going to take some switching activity from simulations and feed those back in.

And those are just some examples of the cool technology because if all you’ve got is a standard power format, that’s a good start, but you really want a lot of technology that can work of that to help the people get the job done and that’s why it’s been a lot of time doing that’s where you waste a lot of time doing is putting them much as the standard format, but the tools and the technology that are needed to make these chips.

Paul Lancour – PodTech

Well, that’s great and as you said this is just an overview. There is a lot of technology here that we can continue to talk about, but perhaps the best thing to do is tell people just to check in at the Website.

Neil Hand – Cadence

Yeah, as you mentioned, there is a lot of technology. You who want to find out more they can go to the cadence.com Website and look at the low-power section there. It’s really exciting to me with this whole area of low-power is that by combining your automation with technology, with standardized formats, we can introduce low-power to a whole range of applications that haven’t been looked at before and so make it possible for devices that can benefit from low-power to adopt it without any of the risks, so it just makes — for me this is just really cool. People should go to the Website find out lots more information because I think which is just going to be a great set of technologies for people who want to work with.

Paul Lancour – PodTech

Well, your excitement about it really comes through and I appreciate you taking the time out to talk to us today.

Neil Hand – Cadence

Thank you very much.

Paul Lancour – PodTech

Neil Hand is the Director of Vertical Solutions Marketing for Cadence.

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