INESC-ID researchers Aleksandar Ilic and Diogo Augusto Pereira Marques reveal their journey in extending Roofline Modeling for use in application optimization, known as the Cache-aware Roofline Model, or CARM, which has been incorporated into the Intel® Advisor tool and recognized with an award from the HiPEAC community in Europe. They are now taking this model further, tackling different types of devices, including CPUs and GPUs, with the help of DPC++. Using CARM, developers can detect bottlenecks in their code and derive strategies to squeeze maximum performance out of their architecture.

Guests:
Aleksandar Ilic, Senior Researcher, HPC Architectures & Systems Group, INESC-ID
Diogo Augusto Pereira Marques, Researcher, HPC Architectures & Systems Group, INESC-ID

To learn more:
Cache-aware Roofline Model paper
Cache-aware Roofline Model Tutorial (oneAPI Dev Summit)
Intel® Advisor
oneAPI

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Tags: Aleksandar Ilic, cache-aware, CPU, cross-architecture, Diogo Augusto Pereira Marques, DPC++, energy efficiency, GPU, heterogeneous, HPC, INESC-ID, Intel Advisor, IST, oneAPI, performance ceiling, performance limit, power, roofline analysis, roofline model, SYCL, Universidad de Lisboa, University of Lisbon
 
Posted in: Audio Podcast, Code Together, Intel