PCI Express* 2.0 Speeds Innovation – Intel Chip Chat – Episode 4

August 2nd, 2007 | Connected Social Media Syndication

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David Fair explains how PCI Express* Gen 2 increases speed, device interoperability and bandwidth. He also provides insight into the Geneseo proposal that Intel and IBM gave to PCI-SIG.

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Tags: bandwidth, David Fair, Geneseo, IBM, Intel, IntelMooresLaw, interoperability, PCI Express, PCI-SIG

Posted in: Connected Social Media, Corporate, Intel, Intel Chip Chat, Intel Developer Forum, Intel Moore's Law

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