From the live webcast at the Clift Hotel in San Francisco on December 2, 2009, Intel CTO Justin Rattner delivers the opening remarks on the Single-Chip Cloud Computer, the latest Intel Labs milestone in the Intel Tera-scale Computing Research Program.
Justin Rattner Keynote Address from Research@Intel Day 2009.
Justin Rattner, 59, is vice president and chief technology officer (CTO). He is also an Intel Senior Fellow and head of Intel Labs. In the latter role, he directs Intel’s global research efforts in microprocessors, systems, and communications including the company’s disruptive research activity.
In 1989, Rattner was named Scientist of the Year by R&D Magazine for his leadership in parallel and distributed computer architecture. In December 1996, Rattner was featured as Person of the Week by ABC World News for his visionary work on the Department of Energy ASCI Red System, the first computer to sustain one trillion operations per second (one teraFLOPS) and the fastest computer in the world between 1996 and 2000. In 1997, Rattner was honored as one of the Computing 200, the 200 individuals having the greatest impact on the U.S. computer industry today, and subsequently profiled in the book Wizards and Their Wonders from ACM Press.
Rattner has received two Intel Achievement Awards for his work in high performance computing and advanced cluster communication architecture. He is a member of the executive committee of the Intel’s Research Council and serves as the Intel executive sponsor for Cornell University where he is a member of the External Advisory Board for the School of Engineering. Rattner is also a trustee of the Anita Borg Institute for Women and Technology.
Rattner joined Intel in 1973. He was named its first Principal Engineer in 1979 and its fourth Intel Fellow in 1988. Prior to joining Intel, Rattner held positions with Hewlett-Packard Company and Xerox Corporation. He holds B.S. and M.S. degrees from Cornell University in electrical engineering and computer science.
At the Intel Developer Forum in San Francisco’s Moscone Center, “Brain Bowl” was an opening night celebration where local and international media got to meet Intel execs and compete in the game of hi-tech trivia hosted by KPIX-TV San Francisco anchor John Kessler.
In this video podcast, you’ll get a taste of the post-competition party, featuring appearances from David “Dadi” Perlmutter, executive VP & general manager of Intel’s Mobility Group, Anand Chandrasekher, senior VP & general manager of Intel’s Ultra Mobility Group, and Justin Rattner, VP, director of Intel’s Corporate Technology Group and Intel’s Chief Technology Officer.
When Intel’s research teams think about the future of computing – from mobile devices with near-limitless functionality to technology for the developing world to virtual worlds and advanced robotics, they are literally mapping our future (a future that could include, for example, a cafe table with networking ability). In this podcast preview of the 2008 Research@Intel Day, to be held at the Computer History Museum in the heart of Silicon Valley, we hear from some of Intel’s key players when it comes to the next generations of technology. Hear what Intel Research is focusing on now from Andrew Chien, vice president, corporate technology group and director of Intel Research; Intel Chief Technology Officer and Director of the Corporate Technology Group Justin Rattner; and Eric Brewer, director, Intel Research Berkeley.
Research Day is a chance to check in Intel on the future impacts that its advanced chip technologies will have on human health, mobility, innovation and, of course, computing – from Terascale architecture, software and programming issues to visual computing challenges.
You can hear more from Andrew Chien, here talking about essential computing, “the vision that drives Intel Research.” Justin Rattner shares some thoughts on virtual words as a precursor to the 3D Internet, and Eric Brewer, also a professor of comptuer science at the University of California, Berkeley, talks about how research from his Berkeley lab could lead to better technologies for the developing world.
Past coverage of Research@Intel Day
Justin Rattner, Intel’s chief technology officer, explores what 3D Web and the rise of virtual communities means for online communication and the technology industry.
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Users are looking for a richer, more cinematic experience from the Internet, according to Justin Rattner, Intel chief technology officer and director, Corporate Technology Group. Rattner gave the final keynote of the Fall IDF in San Francisco, focusing on virtual worlds, which are evolving into what he referred to as the “3-D Internet,” in a keynote titled, “Research and Development: Virtual Worlds – The Rise of the 3D Internet.”
Rattner, who spoke with PodTech’s Michael Johnson to give a preview of the Fall IDF, wrapped up the annual developer conference by acknowledging Wired Magazine’s prediction that, as social media and user-generated content hit the mainstream at the same time as the rise of broadband and increased connectivity (and mobility), the coming year could see 60 million participants in online virtual worlds.
Rattner was also joined onstage by Greg Nuyens, CEO of Qwaq, who demoed virtual worlds for the enterprise. Outside of business applications, virtual surgery (especially as a training tool) suggests that realistic virtual environments are already a significant force in some communities.
The larger message that Rattner left the crowd with was that the computing power that will be necessary to deliver this rich 3-D experience will have to be substantial, especially given the demand that real time or “frame rate” visual experience for the 3D Web will demand.
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Intel CTO Justin Rattner’s candid preview of events at this week’s Intel Developer Forum included an overview of the presentations on Intel’s Penryn and Nehalem processors, and recent progress toward 32 nanometer chip production (and Intel’s efforts to keep up with Moore’s Law).
He also discussed Intel’s work on new rendering via a technology called ray tracing. According to Rattner, there’s a synergy betweeen the ease and increased ability to render using the power of Parallel Computing.
The bottom line from the CTO is that Intel is engaging developers and users in new ways, with the aim of defining what the next generation of paralell and multi-core computing will be like.
Connected Social Media, Corporate, Intel, Intel Developer Forum
Intel@Research Day is a science fair with some unbelievable demos — unbelievable on one hand because some seem to defy physics and on the other hand because the topics under consideration are clearly anthropological. In this podcast, Intel CTO Justin Rattner explains why the company has hired more than a few ethnographers, and he talks about how research at Intel has truly gone global. The featured photo is of a catom, a form of programmable matter called a claytronics atom. Read more about it at www.intel.com/research/dpr.htm.
The day 1 keynotes at the Intel Developer Forum in Beijing featured CTO Justin Rattner and Pat Gelsinger, senior vice president of the Digital Enterprise Group. They talked about new developments at the company. Rattner filled in some detail around Intel’s research efforts (and explained the critical importance of China in these initiatives–the company plans to build a new fab in the northeast-China city of Dalian) as well as offered a lively demonstration of 80-core Tera-scale technology.
Pat Gelsinger, who helped shepherd Tera-scale research, offered insights into the Penryn microprocessor and the products it will power after its release later this year. He also talked about highly parallel, IA programmable architecture codename “Larrabee.” Also in the keynote podcast, Gelsinger unveils QuickAssist Technology to optimize the use of accelerators in servers, and Tolapai to integrate the memory controller, I/O controller hubs and an Intel QuickAssist Technology accelerator into a single processor.
Connected Social Media, Corporate, Intel, Intel Developer Forum, Intel IDF Current
This is a video of Intel engineers talking about their research into 80-core chip technology. PodTech’s interview with Intel CTO Justin Rattner about the company’s 80-core announcement can be found here.
Commissioned by Intel.
Related Stories: IntelMooresLaw
More Information:
Intel Tera-Scale Research (80-Core animation available on this site)
Transcript:
Guest: Nitin Borkar – Intel
Guest: Saurabh Dighe – Intel
Guest: Sriram Vangal – Intel
Nitin Borkar – Intel
Intel’s Teraflop Research Chip consists of lot of innovations going forward for multi-core architectures. Some of them are rapid design conversions, network-on-a-chip and fine-grain power management. Bringing Tera-scale computing to PCs and servers requires a new way of building processors that can be thought of as a network of powerful computers on a chip.
This Teraflop Research Chip is one important example of how the Intel Tera-scale Computing Research Program aims to change the future through constant hardware and software innovations. In addition to the compute element, each core contains a 5-port message passing router. These are connected in a 2D mesh network that implement message-passing protocol. This network on a chip mesh interconnect scheme could prove much more scalable than today’s multi-core interconnect, allowing better connection between the cores.
In the past, you have seen Teraflop computing at the system level. In fact, just 10 years ago, Intel Chip, their first Teraflop machine to Sandia labs, which consisted of multiple cupboards, and that would have probably fit in this room. Today, after 10 years, we’re going to demonstrate Intel’s technical leadership and manufacturing capability. We’re embedding that same performance in this chip.
Saurabh Dighe – Intel
What we have here first is this custom made board, was designed in this lab. The other thing is the chip is sitting right underneath this chiller head, they’ve got these cables providing the supply to the board. Each cable here provides 50 amps. The cables here are the J-Tech controls and the input-output of the chip.
Sriram Vangal – Intel
Hi, the display on the left side shows 80 tiles on a single chip with each tile consisting of dual floating point engines and an on-dial router responsible for communication between the tiles. So, the maximum achieved frequency on this chip is 5 gigahertz, and with all 80 tiles running a blocked matrix version, the peak performance on the — observe this, 1.6 Teraflops.
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