Intel Scientists Talk Tereflops
This is a video of Intel engineers talking about their research into 80-core chip technology. PodTech’s interview with Intel CTO Justin Rattner about the company’s 80-core announcement can be found here.
Commissioned by Intel.
Related Stories: IntelMooresLaw
More Information:
Intel Tera-Scale Research (80-Core animation available on this site)
Transcript:
Guest: Nitin Borkar – Intel
Guest: Saurabh Dighe – Intel
Guest: Sriram Vangal – Intel
Nitin Borkar – Intel
Intel’s Teraflop Research Chip consists of lot of innovations going forward for multi-core architectures. Some of them are rapid design conversions, network-on-a-chip and fine-grain power management. Bringing Tera-scale computing to PCs and servers requires a new way of building processors that can be thought of as a network of powerful computers on a chip.
This Teraflop Research Chip is one important example of how the Intel Tera-scale Computing Research Program aims to change the future through constant hardware and software innovations. In addition to the compute element, each core contains a 5-port message passing router. These are connected in a 2D mesh network that implement message-passing protocol. This network on a chip mesh interconnect scheme could prove much more scalable than today’s multi-core interconnect, allowing better connection between the cores.
In the past, you have seen Teraflop computing at the system level. In fact, just 10 years ago, Intel Chip, their first Teraflop machine to Sandia labs, which consisted of multiple cupboards, and that would have probably fit in this room. Today, after 10 years, we’re going to demonstrate Intel’s technical leadership and manufacturing capability. We’re embedding that same performance in this chip.
Saurabh Dighe – Intel
What we have here first is this custom made board, was designed in this lab. The other thing is the chip is sitting right underneath this chiller head, they’ve got these cables providing the supply to the board. Each cable here provides 50 amps. The cables here are the J-Tech controls and the input-output of the chip.
Sriram Vangal – Intel
Hi, the display on the left side shows 80 tiles on a single chip with each tile consisting of dual floating point engines and an on-dial router responsible for communication between the tiles. So, the maximum achieved frequency on this chip is 5 gigahertz, and with all 80 tiles running a blocked matrix version, the peak performance on the — observe this, 1.6 Teraflops.
Copyright ©2006 PodTech.net. All rights reserved. Privacy policy
Posted in:
Connected Social Media, Corporate, Intel, Intel Moore's Law, Intel PCA Past and Future, Technology
