High-Performance Computing For Silicon Design

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High-Performance Computing For Silicon Design
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IT Best Practices: Designing Intel microprocessors is extremely compute intensive. Tapeout is a final step in silicon design and its computation demand is growing exponentially for each generation of silicon process technology. Intel IT adopted high-performance computing (HPC) to address this very large computational scale and realized significant improvements in computing performance, reliability, and cost. We treated the HPC environment as a holistic computing capability—ensuring all key components were well designed, integrated, and operationally balanced with no bottlenecks. We designed our HPC model to scale to meet future needs, with HPC generations aligned with successive generations of Intel process technology.

The first-generation HPC environment (HPC-1), supporting 45nm processor tapeout, included innovative approaches and technologies to increase scalability. HPC-1 successfully enabled 45nm processor tapeout, delivering net present value (NPV) of USD 44.72 million to Intel. We subsequently developed three new generations of HPC environment (HPC-2, HPC-3, and HPC-4), with further scalability increases to support the tapeout of 32nm, 22nm, and 14nm processors, respectively.

Since deployment, our HPC environment has supported a 29.87x increase in compute demand, with a 20x increase in stability. In addition, tapeout time was reduced from 25 days for the first 65nm process technology-based microprocessor in a non-HPC compute environment to 10 days for the first 45nm process technology-based microprocessor in an HPC-enabled environment. The success of the HPC environment was due to factors such as careful alignment of technology with business needs, informed risk taking, and disciplined execution. We are continuing to develop the next HPC generations to enable tapeout of successive generations of Intel processors.


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